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authorFred Reitberger <reitbergerfred@gmail.com>2022-10-17 11:49:55 -0400
committerFelix Held <felix-coreboot@felixheld.de>2022-10-18 16:09:44 +0000
commit13831223bec0fada21a703fa23b06663942f11de (patch)
treeb6de37653ca1a965e7df16fbed4d88b72ec15fe6 /src/soc/amd/stoneyridge
parentf2b36036c7b2906071543a8c9590fdbb0f53dfc9 (diff)
soc/amd/*/i2c: Move reset_i2c_peripherals to i2c.c
Move i2c SoC related code from early_fch.c to i2c.c TEST=build boards for each SoC Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/early_fch.c19
-rw-r--r--src/soc/amd/stoneyridge/i2c.c19
-rw-r--r--src/soc/amd/stoneyridge/include/soc/i2c.h2
3 files changed, 21 insertions, 19 deletions
diff --git a/src/soc/amd/stoneyridge/early_fch.c b/src/soc/amd/stoneyridge/early_fch.c
index 5a8de13e20..b46bde787f 100644
--- a/src/soc/amd/stoneyridge/early_fch.c
+++ b/src/soc/amd/stoneyridge/early_fch.c
@@ -12,14 +12,6 @@
#include "chip.h"
-/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
-static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
- I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
- I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
- I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
- I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
-};
-
static void sb_lpc_decode(void)
{
u32 tmp = 0;
@@ -111,17 +103,6 @@ static void setup_misc(int *reboot)
}
}
-static void reset_i2c_peripherals(void)
-{
- const struct soc_amd_stoneyridge_config *cfg = config_of_soc();
- struct soc_i2c_peripheral_reset_info reset_info;
-
- reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
- reset_info.i2c_scl = i2c_scl_pins;
- reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
- sb_reset_i2c_peripherals(&reset_info);
-}
-
/* Before console init */
void bootblock_fch_early_init(void)
{
diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
index e589b04f78..f7adbecadf 100644
--- a/src/soc/amd/stoneyridge/i2c.c
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -7,6 +7,14 @@
#include "chip.h"
#include <drivers/i2c/designware/dw_i2c.h>
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
+static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
+ I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
+ I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
+ I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
+ I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
+};
+
static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = {
{ I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" },
{ I2C_MASTER_MODE, APU_I2C1_BASE, "I2CB" },
@@ -14,6 +22,17 @@ static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = {
{ I2C_MASTER_MODE, APU_I2C3_BASE, "I2CD" },
};
+void reset_i2c_peripherals(void)
+{
+ const struct soc_amd_stoneyridge_config *cfg = config_of_soc();
+ struct soc_i2c_peripheral_reset_info reset_info;
+
+ reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ reset_info.i2c_scl = i2c_scl_pins;
+ reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
+ sb_reset_i2c_peripherals(&reset_info);
+}
+
const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
{
*num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h
index b16084b5ad..505802e5f1 100644
--- a/src/soc/amd/stoneyridge/include/soc/i2c.h
+++ b/src/soc/amd/stoneyridge/include/soc/i2c.h
@@ -22,4 +22,6 @@
#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
+void reset_i2c_peripherals(void);
+
#endif /* AMD_STONEYRIDGE_I2C_H */