mb/google/kahlee: Tune eDP panel initialization time

1. Add two parameters for panel initialization timing.
   > lvds_poseq_varybl_to_blon
   > lvds_poseq_blon_to_varybl
2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/
   EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage,
   and be enabled depends on SKU, thus we can control the delay
   time by config APU_DP_VARY_BL.

BUG=b:118011567
TEST=emerge-grunt coreboot.

Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 320bef0bdf..92223d1962 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -63,6 +63,15 @@ struct soc_amd_stoneyridge_config {
 	u8 stapm_percent;
 	u32 stapm_time_ms;
 	u32 stapm_power_mw;
+	/*
+	 * This specifies the LVDS/eDP power-up sequence time for the delay
+	 * between VaryBL and BLON.
+	 * 0 - Use the VBIOS default (default). The video BIOS default is 32ms.
+	 * n - Values other than zero specify a setting of (4 * n) milliseconds
+	 *     time delay.
+	 */
+	u8 lvds_poseq_varybl_to_blon;
+	u8 lvds_poseq_blon_to_varybl;
 };
 
 typedef struct soc_amd_stoneyridge_config config_t;