soc/amd: Standardize guards on header files

The guards in the header files were inconsistent. Some had no leading or
trailing underscores, some had one, some had both leading and trailing.

Change all to double leading & trailing underscores.
Change all comments to have a space before them instead of tabs

BUG=b:62235990
Test=Build Kahlee

Change-Id: I4466df529ab201c922096a31d7438381778b582f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

12 files changed, 35 insertions, 35 deletions

diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 747c2956f1..cd3bc74d90 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_CHIP_H
-#define STONEYRIDGE_CHIP_H
+#ifndef __STONEYRIDGE_CHIP_H__
+#define __STONEYRIDGE_CHIP_H__
 
 #include <stdint.h>
 
@@ -32,4 +32,4 @@ typedef struct soc_amd_stoneyridge_config config_t;
 
 extern struct device_operations pci_domain_ops;
 
-#endif /* STONEYRIDGE_CHIP_H */
+#endif /* __STONEYRIDGE_CHIP_H__ */
diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
index f3f60d3b61..a8e75f6327 100644
--- a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef AMD_PCI_INT_DEFS_H
-#define AMD_PCI_INT_DEFS_H
+#ifndef __AMD_PCI_INT_DEFS_H__
+#define __AMD_PCI_INT_DEFS_H__
 
 /*
  * PIRQ and device routing - these define the index
@@ -72,4 +72,4 @@
 #define PIRQ_UART0	0x74
 #define PIRQ_UART1	0x75
 
-#endif /* AMD_PCI_INT_DEFS_H */
+#endif /* __AMD_PCI_INT_DEFS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
index ab1f70b869..08bdc108cf 100644
--- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef AMD_PCI_INT_TYPES_H
-#define AMD_PCI_INT_TYPES_H
+#ifndef __AMD_PCI_INT_TYPES_H__
+#define __AMD_PCI_INT_TYPES_H__
 
 const char *intr_types[] = {
 	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t",
@@ -34,4 +34,4 @@ const char *intr_types[] = {
 	[0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t",
 };
 
-#endif /* AMD_PCI_INT_TYPES_H */
+#endif /* __AMD_PCI_INT_TYPES_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
index f573b0ed81..3e58d9a0c7 100644
--- a/src/soc/amd/stoneyridge/include/soc/acpi.h
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_STONEYRIDGE_ACPI_H_
-#define _SOC_STONEYRIDGE_ACPI_H_
+#ifndef __SOC_STONEYRIDGE_ACPI_H__
+#define __SOC_STONEYRIDGE_ACPI_H__
 
 #include <arch/acpi.h>
 
@@ -35,4 +35,4 @@ unsigned long southbridge_write_acpi_tables(device_t device,
 
 void southbridge_inject_dsdt(device_t device);
 
-#endif	/* _SOC_STONEYRIDGE_ACPI_H_ */
+#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index c43dd2767a..c5b7c8a4d4 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _STONEYRIDGE_GPIO_H_
-#define _STONEYRIDGE_GPIO_H_
+#ifndef __STONEYRIDGE_GPIO_H__
+#define __STONEYRIDGE_GPIO_H__
 
 #include <soc/amd/common/amd_defs.h>
 #include <types.h>
@@ -129,4 +129,4 @@
 
 typedef uint32_t gpio_t;
 
-#endif	/* _STONEYRIDGE_GPIO_H_ */
+#endif /* __STONEYRIDGE_GPIO_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/imc.h b/src/soc/amd/stoneyridge/include/soc/imc.h
index a077506ff3..d61340941c 100644
--- a/src/soc/amd/stoneyridge/include/soc/imc.h
+++ b/src/soc/amd/stoneyridge/include/soc/imc.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_IMC_H
-#define STONEYRIDGE_IMC_H
+#ifndef __STONEYRIDGE_IMC_H__
+#define __STONEYRIDGE_IMC_H__
 
 void imc_reg_init(void);
 void enable_imc_thermal_zone(void);
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index e082a9d067..13d7d36270 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef PI_STONEYRIDGE_NORTHBRIDGE_H
-#define PI_STONEYRIDGE_NORTHBRIDGE_H
+#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
+#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
 
 #include <arch/cpu.h>
 #include <arch/io.h>
@@ -30,4 +30,4 @@ void setup_uma_memory(void);
 /* todo: remove this when postcar stage is in place */
 asmlinkage void chipset_teardown_car(void);
 
-#endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */
+#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index b28f386ec8..68763a94de 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef _SOC_STONEYRIDGE_NVS_H_
-#define _SOC_STONEYRIDGE_NVS_H_
+#ifndef __SOC_STONEYRIDGE_NVS_H__
+#define __SOC_STONEYRIDGE_NVS_H__
 
 #include <stdint.h>
 #include <vendorcode/google/chromeos/gnvs.h>
@@ -48,4 +48,4 @@ typedef struct global_nvs_t {
 	chromeos_acpi_t chromeos;
 } __attribute__((packed)) global_nvs_t;
 
-#endif	/* _SOC_STONEYRIDGE_NVS_H_ */
+#endif /* __SOC_STONEYRIDGE_NVS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
index 8bea376f64..5c7f86a8c7 100644
--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _PI_STONEYRIDGE_PCI_DEVS_H_
-#define _PI_STONEYRIDGE_PCI_DEVS_H_
+#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
+#define __PI_STONEYRIDGE_PCI_DEVS_H__
 
 #include <device/pci_def.h>
 #include <rules.h>
@@ -285,4 +285,4 @@
 #define SD_DEVID		0x7906
 #define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
 
-#endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */
+#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h
index c9b19e5fc2..90a59e4743 100644
--- a/src/soc/amd/stoneyridge/include/soc/smbus.h
+++ b/src/soc/amd/stoneyridge/include/soc/smbus.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_SMBUS_H
-#define STONEYRIDGE_SMBUS_H
+#ifndef __STONEYRIDGE_SMBUS_H__
+#define __STONEYRIDGE_SMBUS_H__
 
 #include <stdint.h>
 
@@ -67,4 +67,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
 void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
 
-#endif	/* STONEYRIDGE_SMBUS_H */
+#endif /* __STONEYRIDGE_SMBUS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 193fb0ced3..46004c9a31 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -5,8 +5,8 @@
  * Subject to the GNU GPL v2, or (at your option) any later version.
  */
 
-#ifndef _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H
-#define _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H
+#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
+#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
 
 #include <arch/io.h>
 
@@ -62,4 +62,4 @@ void enable_acpi_cmd_smi(void);
 void enable_smi_generation(void);
 #endif
 
-#endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */
+#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index de481f0eea..20edf5f4cc 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_H
-#define STONEYRIDGE_H
+#ifndef __STONEYRIDGE_H__
+#define __STONEYRIDGE_H__
 
 #include <arch/io.h>
 #include <types.h>
@@ -204,4 +204,4 @@ void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 void bootblock_fch_early_init(void);
 
-#endif /* STONEYRIDGE_H */
+#endif /* __STONEYRIDGE_H__ */