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authorFelix Held <felix-coreboot@felixheld.de>2020-12-11 15:51:51 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-13 22:18:50 +0000
commit815efe16cb6916334866084c921431a5be4157df (patch)
tree420dd30745061df94d9157eb30580ff1e9a98f08 /src/soc/amd/stoneyridge
parent4bbcf60556ee9483b34b6040f25852a30264b09c (diff)
soc/amd/*/include/spc/gpio: fix pin numbers in comments
Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 8bfb1f606b..714d219628 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -14,7 +14,7 @@
#define SOC_GPIO_TOTAL_PINS 149
-/* Bank 0: GPIO_0 - GPIO_62 */
+/* Bank 0: GPIO_0 - GPIO_63 */
#define GPIO_0 0
#define GPIO_1 1
#define GPIO_2 2
@@ -89,7 +89,7 @@
#define GPIO_122 122
#define GPIO_126 126
-/* Bank 2: GPIO_128 - GPIO_183 */
+/* Bank 2: GPIO_128 - GPIO_191 */
#define GPIO_129 129
#define GPIO_130 130
#define GPIO_131 131