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authorAaron Durbin <adurbin@chromium.org>2020-08-14 16:22:11 -0600
committerAaron Durbin <adurbin@chromium.org>2020-08-17 17:40:11 +0000
commit5a5e4d05ebd4cf543c1704e5e8ba36523697be2e (patch)
tree776b9018e447f1084e0f95c4b5b38e14d1ff37c0 /src/soc/amd/stoneyridge
parenta244eb3dad1e81a1a7d15cf43ca7f622345ac230 (diff)
soc/amd/stoneyridge: use new ACPI helper functions from common
Transition the current call sequence to using the newly added common ACPI helper functions. Semantically, the expectations are that this sequence is the equivalent of previous acpi_clear_pm1_status(). BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c51
1 files changed, 14 insertions, 37 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 628aea993b..267f747b4f 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -501,59 +501,36 @@ static void sb_init_acpi_ports(void)
PM_ACPI_TIMER_EN_EN);
}
-static int get_index_bit(uint32_t value, uint16_t limit)
-{
- uint16_t i;
- uint32_t t;
-
- if (limit >= TOTAL_BITS(uint32_t))
- return -1;
-
- /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */
- t = (1 << limit) - 1;
- if ((value & t) == 0)
- return -1;
- t = 1;
- for (i = 0; i < limit; i++) {
- if (value & t)
- break;
- t <<= 1;
- }
- return i;
-}
-
static void set_nvs_sws(void *unused)
{
- struct soc_power_reg *sws;
+ struct acpi_pm_gpe_state *state;
struct global_nvs *gnvs;
- int index;
- sws = cbmem_find(CBMEM_ID_POWER_STATE);
- if (sws == NULL)
+ state = cbmem_find(CBMEM_ID_POWER_STATE);
+ if (state == NULL)
return;
gnvs = acpi_get_gnvs();
if (gnvs == NULL)
return;
- index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT);
- if (index < 0)
- gnvs->pm1i = ~0ULL;
- else
- gnvs->pm1i = index;
-
- index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT);
- if (index < 0)
- gnvs->gpei = ~0ULL;
- else
- gnvs->gpei = index;
+ acpi_fill_gnvs(gnvs, state);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
void southbridge_init(void *chip_info)
{
+ struct acpi_pm_gpe_state *state;
+
sb_init_acpi_ports();
- acpi_clear_pm1_status();
+
+ state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
+ if (state) {
+ acpi_fill_pm_gpe_state(state);
+ acpi_pm_gpe_add_events_print_events(state);
+ }
+
+ acpi_clear_pm_gpe_status();
}
static void set_sb_final_nvs(void)