soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart

The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So  configure_stoneyridge_uart()
became redundant. Remove procedure  configure_stoneyridge_uart().

BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.

Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 12 deletions

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index cf059a46b2..55e39569d0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -36,9 +36,7 @@
  * Table of devices that need their AOAC registers enabled and waited
  * upon (usually about .55 milliseconds). Instead of individual delays
  * waiting for each device to become available, a single delay will be
- * executed at configure_stoneyridge_uart(). All other devices need only
- * to verify if their AOAC is already enabled, and do a minimal delay
- * if needed.
+ * executed.
  */
 const static struct stoneyridge_aoac aoac_devs[] = {
 	{ (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
@@ -331,15 +329,6 @@ void enable_aoac_devices(void)
 	} while (!status);
 }
 
-void configure_stoneyridge_uart(void)
-{
-	/* Set the GPIO mux to UART */
-	write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
-	write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
-	write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
-	write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
-}
-
 void sb_pci_port80(void)
 {
 	u8 byte;