amd/stoneyridge: Create new name/IRQ association

Table intr_types[] is hard to maintain, and has unused spaces filled with
NULL. A new table format is needed that creates strong association between
the APIC register index and the associated IRQ name, is easy to maintain
and has no unused space (index) to indicate that a particular register is
unused while still indicating which registers are valid.

Also, the string that defines the name of associated IRQ should be declared
with "#define" in a header, but must be physically initiated in a source
file. The "#define" must make a strong association between the used register
index and the associated IRQ name. Example:
#define INDEX_0X16_NAME "PerMon\t"

BUG=b:69868534
TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh
Processors definitions for Pci_Intr_Index. Also, check for new output
format to confirm write_pci_int_table() is working as desired. There's
no test for write_pci_cfg_irqs, as it's not being used by kahlee.

Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 58 insertions, 1 deletions

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index dbf27bc6b8..44dbf62a1c 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010-2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -27,10 +27,67 @@
 #include <amd_pci_util.h>
 #include <soc/southbridge.h>
 #include <soc/smi.h>
+#include <soc/amd_pci_int_defs.h>
 #include <fchec.h>
 #include <delay.h>
 #include <soc/pci_devs.h>
 
+/*
+ * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
+ * provides a visible association with the index, therefor helping
+ * maintainability of table. If a new index/name is defined in
+ * amd_pci_int_defs.h, just add the pair at the end of this table.
+ * Order is not important.
+ */
+const static struct irq_idx_name irq_association[] = {
+	{ PIRQ_A,	"INTA#\t" },
+	{ PIRQ_B,	"INTB#\t" },
+	{ PIRQ_C,	"INTC#\t" },
+	{ PIRQ_D,	"INTD#\t" },
+	{ PIRQ_E,	"INTE#\t" },
+	{ PIRQ_F,	"INTF#\t" },
+	{ PIRQ_G,	"INTG#\t" },
+	{ PIRQ_H,	"INTH#\t" },
+	{ PIRQ_MISC,	"Misc\t" },
+	{ PIRQ_MISC0,	"Misc0\t" },
+	{ PIRQ_MISC1,	"Misc1\t" },
+	{ PIRQ_MISC2,	"Misc2\t" },
+	{ PIRQ_SIRQA,	"Ser IRQ INTA" },
+	{ PIRQ_SIRQB,	"Ser IRQ INTB" },
+	{ PIRQ_SIRQC,	"Ser IRQ INTC" },
+	{ PIRQ_SIRQD,	"Ser IRQ INTD" },
+	{ PIRQ_SCI,	"SCI\t" },
+	{ PIRQ_SMBUS,	"SMBUS\t" },
+	{ PIRQ_ASF,	"ASF\t" },
+	{ PIRQ_HDA,	"HDA\t" },
+	{ PIRQ_FC,	"FC\t\t" },
+	{ PIRQ_PMON,	"PerMon\t" },
+	{ PIRQ_SD,	"SD\t\t" },
+	{ PIRQ_SDIO,	"SDIO\t" },
+	{ PIRQ_IMC0,	"IMC INT0\t" },
+	{ PIRQ_IMC1,	"IMC INT1\t" },
+	{ PIRQ_IMC2,	"IMC INT2\t" },
+	{ PIRQ_IMC3,	"IMC INT3\t" },
+	{ PIRQ_IMC4,	"IMC INT4\t" },
+	{ PIRQ_IMC5,	"IMC INT5\t" },
+	{ PIRQ_EHCI,	"EHCI\t" },
+	{ PIRQ_XHCI,	"XHCI\t" },
+	{ PIRQ_SATA,	"SATA\t" },
+	{ PIRQ_GPIO,	"GPIO\t" },
+	{ PIRQ_I2C0,	"I2C0\t" },
+	{ PIRQ_I2C1,	"I2C1\t" },
+	{ PIRQ_I2C2,	"I2C2\t" },
+	{ PIRQ_I2C3,	"I2C3\t" },
+	{ PIRQ_UART0,	"UART0\t" },
+	{ PIRQ_UART1,	"UART1\t" },
+};
+
+const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
+{
+	*size = ARRAY_SIZE(irq_association);
+	return irq_association;
+}
+
 void configure_stoneyridge_uart(void)
 {
 	u8 byte, byte2;