diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-10-05 15:41:03 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-12 15:13:32 +0000 |
| commit | ecce847606e18aace9fde5f925a7a3a6a85181ee (patch) | |
| tree | 897232e4ad2720821e2c429632982c13794d4dde /src/soc/amd/stoneyridge/southbridge.c | |
| parent | 10509c6f190c791d4e06006610dd83200c9fad37 (diff) | |
amd/stoneyridge: Convert hex definitions to lower case
Match the rest of the soc/stoneyridge source.
Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 763ddd7481..7f0318a80a 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -578,14 +578,14 @@ static void setup_spread_spectrum(int *reboot) uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); cfg6 &= ~CG1PLL_LF_MODE_MASK; - cfg6 |= (0x0F8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; + cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; misc_write32(MISC_CGPLL_CONFIG6, cfg6); uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); cfg3 &= ~CG1PLL_REFDIV_MASK; cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; cfg3 &= ~CG1PLL_FBDIV_MASK; - cfg3 |= (0x04B << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; + cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; misc_write32(MISC_CGPLL_CONFIG3, cfg3); uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); @@ -595,9 +595,9 @@ static void setup_spread_spectrum(int *reboot) uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK; - cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xd000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; - cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02d5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; misc_write32(MISC_CGPLL_CONFIG4, cfg4); rstcfg |= TOGGLE_ALL_PWR_GOOD; |