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authorFelix Held <felix-coreboot@felixheld.de>2021-01-29 16:01:10 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-30 17:17:48 +0000
commita21690ba1276f94365a685fa04901e0273c426bd (patch)
treebd818b575eb51f9b03e47e487c57e62999cb6cc4 /src/soc/amd/stoneyridge/southbridge.c
parentffc87e9cbe1a811332de6a87186e9c3ad3755709 (diff)
soc/amd/stoneyridge/southbridge: replace southbridge prefix with fch
This aligns the function names with Picasso and Cezanne. Also move the fch_* functions in the header file in the order they get called. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49db8021edae5e537f043bf52eea1be54dc46eca Reviewed-on: https://review.coreboot.org/c/coreboot/+/50124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 11791f2b62..2a915965bb 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -402,7 +402,7 @@ static void sb_init_acpi_ports(void)
PM_ACPI_TIMER_EN_EN);
}
-void southbridge_init(void *chip_info)
+void fch_init(void *chip_info)
{
struct chipset_power_state *state;
@@ -461,7 +461,7 @@ static void set_sb_gnvs(struct global_nvs *gnvs)
& ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
}
-void southbridge_final(void *chip_info)
+void fch_final(void *chip_info)
{
uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;