diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2018-06-28 16:31:45 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-02 07:35:00 +0000 |
| commit | 5b058233882eefc100e4ca49b4bdbedffe395356 (patch) | |
| tree | b42acc09847c2f376e392c5fd270ae37039eb08b /src/soc/amd/stoneyridge/southbridge.c | |
| parent | 6756c16e82728ce612a333017bf23f5a497f554f (diff) | |
stoneyridge: Enable IO CF9 in bootblock
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or
verstage.
BUG=b:110817463
TEST=built on grunt and made sure that hard_reset() reboots.
Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27267
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c46bcb44a6..591a8f7c9f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -368,6 +368,13 @@ void sb_acpi_mmio_decode(void) outb(byte, PM_DATA); } +static void sb_enable_cf9_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -542,6 +549,7 @@ void bootblock_fch_early_init(void) sb_spibase(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); + sb_enable_cf9_io(); enable_aoac_devices(); } |