diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-10-22 13:57:18 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-30 16:57:53 +0000 |
| commit | 41baf0c3ff8bf23a154eb6505c4e254f5bdc253b (patch) | |
| tree | e643d364058d032964026e60f01eda512bbd4f6b /src/soc/amd/stoneyridge/southbridge.c | |
| parent | 58bf3e763297d658ed83dd35b30293dfab3e135f (diff) | |
soc/amd/stoneyridge: Remove dev_find_slot where possible
The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.
BUG=b:117917136
TEST=Build grunt.
Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 326ea613b0..35cf253b7b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -892,7 +892,7 @@ static void set_sb_final_nvs(void) uintptr_t xhci_fw; uintptr_t fwaddr; size_t fwsize; - const struct device *sd, *sata, *ehci; + const struct device *sd, *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs == NULL) @@ -925,7 +925,6 @@ static void set_sb_final_nvs(void) gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; gnvs->fw03 = fwsize << 16; - ehci = dev_find_slot(0, EHCI1_DEVFN); gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } |