stoneyridge GPIO: Create and use PAD_INT for interrupt pins

The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.

BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.

Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 0 insertions, 21 deletions

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 5a3a442415..cc21601c3e 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -173,27 +173,6 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
 	return irq_association;
 }
 
-void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr, size_t size)
-{
-	void *tmp_ptr;
-	uint8_t control, mux, index;
-
-	for (index = 0; index < size; index++) {
-		mux = gpio_ptr[index].function;
-		control = gpio_ptr[index].control;
-		tmp_ptr = (void *)(gpio_ptr[index].gpio + AMD_GPIO_MUX);
-		write8(tmp_ptr, mux & AMD_GPIO_MUX_MASK);
-
-		/*
-		 * Get the address of AMD_GPIO_CONTROL (dword) relative
-		 * to the desired pin and program bits 16-23.
-		 */
-		tmp_ptr = (void *)(gpio_ptr[index].gpio * sizeof(uint32_t) +
-					AMD_GPIO_CONTROL + 2);
-		write8(tmp_ptr, control);
-	}
-}
-
 /**
  * @brief Find the size of a particular wide IO
  *