diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-10-05 19:01:52 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-12 15:16:52 +0000 |
| commit | edba21e4a64f87308a4a1725aaeaf5cc7f62797b (patch) | |
| tree | e474441b4f49d0b506368310272c96d32efd6acb /src/soc/amd/stoneyridge/southbridge.c | |
| parent | d1aa8eba72c640e94ef410bbb0f37c35ee8c9a5c (diff) | |
amd/stoneyridge: Rename CGPLL_CONFIG definitions
Shorten the names in the MISC CGPLL_CONFIG, and make the formatting match
the surrounding source.
Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7f0318a80a..b7ddd578d6 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -589,15 +589,16 @@ static void setup_spread_spectrum(int *reboot) misc_write32(MISC_CGPLL_CONFIG3, cfg3); uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); - cfg5 &= ~CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; - cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; misc_write32(MISC_CGPLL_CONFIG5, cfg5); uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); - cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK; - cfg4 |= (0xd000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; - cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; - cfg4 |= (0x02d5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; + cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; + cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) + & SS_STEP_SIZE_DSFRAC_MASK; misc_write32(MISC_CGPLL_CONFIG4, cfg4); rstcfg |= TOGGLE_ALL_PWR_GOOD; |