diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-01 17:33:42 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-05-08 13:49:45 +0000 |
| commit | b4b9efcfdd47efe67b13e1cf8cfea2ffe08fb012 (patch) | |
| tree | e701ef4e442478ab8ce9457f126c0d1a016e07f4 /src/soc/amd/stoneyridge/southbridge.c | |
| parent | b435d4405dacdc218777aaba349151ae28997741 (diff) | |
soc/amd/stoneyridge: Finish read/write misc registers
Add 16 and 32-bit versions of read / write_misc functions. Find one
access of the MISC block still using read8() and write8(), and convert
it.
Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7dc27c86da..b5901782f6 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -391,14 +391,12 @@ static void sb_enable_legacy_io(void) void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; - u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(ACPIMMIO_MISC_BASE - + MISC_CLK_CNTL1); /* * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. */ - ctrl = read32(misc_clk_cntl_1_ptr); + ctrl = misc_read32(MISC_CLK_CNTL1); switch (osc) { case 1: @@ -410,7 +408,7 @@ void sb_clk_output_48Mhz(u32 osc) default: return; /* do nothing if invalid */ } - write32(misc_clk_cntl_1_ptr, ctrl); + misc_write32(MISC_CLK_CNTL1, ctrl); } static uintptr_t sb_spibase(void) |