diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-05 15:39:40 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-05-10 17:35:18 +0000 |
| commit | 939bfccb3dbf04a0a2f7e15b82db1fdb469b7a73 (patch) | |
| tree | c19c99337abf8416866d32f3430bb43df8439592 /src/soc/amd/stoneyridge/southbridge.c | |
| parent | f36fcdf2ab6a9956ac60012404e0edf1d6653fac (diff) | |
soc/amd/stoneyridge: Add IO access functions for PMx
Replace locations in the source that explicitely use the CD6/CD7
index/data pair with utility function calls.
Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b5901782f6..8dfef8b369 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -329,11 +329,9 @@ void sb_lpc_port80(void) u8 byte; /* Enable LPC controller */ - outb(PM_LPC_GATING, PM_INDEX); - byte = inb(PM_DATA); + byte = pm_io_read8(PM_LPC_GATING); byte |= PM_LPC_ENABLE; - outb(PM_LPC_GATING, PM_INDEX); - outb(byte, PM_DATA); + pm_io_write8(PM_LPC_GATING, byte); /* Enable port 80 LPC decode in pci function 3 configuration space. */ byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); @@ -367,11 +365,9 @@ void sb_acpi_mmio_decode(void) uint8_t byte; /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ - outb(PM_ISA_CONTROL, PM_INDEX); - byte = inb(PM_DATA); + byte = pm_io_read8(PM_ISA_CONTROL); byte |= MMIO_EN; - outb(PM_ISA_CONTROL, PM_INDEX); - outb(byte, PM_DATA); + pm_io_write8(PM_ISA_CONTROL, byte); } static void sb_enable_cf9_io(void) |