diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-10-17 13:32:58 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:49:43 +0000 |
| commit | 6205221a7375f5b54ddee77b303915c593c35599 (patch) | |
| tree | 4245b83da19cb639a1e3779d390a7d2b855d9fa6 /src/soc/amd/stoneyridge/southbridge.c | |
| parent | e7e01116e72205113243e43b0ca1bed4c584c5b3 (diff) | |
soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40
Register 0x40 of miscellaneous MMIO is double defined, with different names,
which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only
bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO
registers.
BUG=b:117818431
TEST=Build grunt.
Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/southbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 33330a8812..37ebdc115d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -395,7 +395,7 @@ void sb_clk_output_48Mhz(void) { u32 ctrl; u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE - + MISC_MISC_CLK_CNTL_1); + + MISC_CLK_CNTL1); /* * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so |