soc: Add AMD Stoney Ridge southbridge code

Copy the Hudson/Kern code from southbridge/amd/pi/hudson.  This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/

Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops

Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 78 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c
new file mode 100644
index 0000000000..fecaf90723
--- /dev/null
+++ b/src/soc/amd/stoneyridge/smi_util.c
@@ -0,0 +1,78 @@
+/*
+ * SMM utilities used in both SMM and normal mode
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <console/console.h>
+#include <soc/smi.h>
+
+#define STONEYRIDGE_SMI_ACPI_COMMAND		75
+
+static void configure_smi(uint8_t smi_num, uint8_t mode)
+{
+	uint8_t reg32_offset, bit_offset;
+	uint32_t reg32;
+
+	/* SMI sources range from [0:149] */
+	if (smi_num > 149) {
+		printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num);
+		return;
+	}
+
+	/* 16 sources per register, 2 bits per source; registers are 4 bytes */
+	reg32_offset = (smi_num / 16) * 4;
+	bit_offset = (smi_num % 16) * 2;
+
+	reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset);
+	reg32 &= ~(0x3 << (bit_offset));
+	reg32 |= (mode & 0x3) << bit_offset;
+	smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32);
+}
+
+/**
+ * Configure generation of interrupts for given GEVENT pin
+ *
+ * @param gevent The GEVENT pin number. Valid values are 0 thru 23
+ * @param mode The type of event this pin should generate. Note that only
+ *	       SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events.
+ * @param level SMI_LVL_LOW or SMI_LVL_HIGH
+ */
+void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
+{
+	uint32_t reg32;
+	/* GEVENT pins range from [0:23] */
+	if (gevent > 23) {
+		printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent);
+		return;
+	}
+
+	/* SMI0 source is GEVENT0 and so on */
+	configure_smi(gevent, mode);
+
+	/* And set set the trigger level */
+	reg32 = smi_read32(SMI_REG_SMITRIG0);
+	reg32 &= ~(1 << gevent);
+	reg32 |= (level & 0x1) << gevent;
+	smi_write32(SMI_REG_SMITRIG0, reg32);
+}
+
+/** Disable events from given GEVENT pin */
+void hudson_disable_gevent_smi(uint8_t gevent)
+{
+	/* GEVENT pins range from [0:23] */
+	if (gevent > 23) {
+		printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent);
+		return;
+	}
+
+	/* SMI0 source is GEVENT0 and so on */
+	configure_smi(gevent, SMI_MODE_DISABLE);
+}
+
+/** Enable SMIs on writes to ACPI SMI command port */
+void hudson_enable_acpi_cmd_smi(void)
+{
+	configure_smi(STONEYRIDGE_SMI_ACPI_COMMAND, SMI_MODE_SMI);
+}