soc: Add AMD Stoney Ridge southbridge code

Copy the Hudson/Kern code from southbridge/amd/pi/hudson.  This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/

Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops

Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 26 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
new file mode 100644
index 0000000000..c92697cf6d
--- /dev/null
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -0,0 +1,26 @@
+/*
+ * Utilities for SMM setup
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <soc/smi.h>
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+	printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n");
+}
+
+/** Set the EOS bit and enable SMI generation from southbridge */
+void hudson_enable_smi_generation(void)
+{
+	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
+	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
+	reg |= SMITRG0_EOS;	/* Set EOS bit */
+	smi_write32(SMI_REG_SMITRIG0, reg);
+}