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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-05-03 20:29:32 -0600
committerMartin Roth <martinroth@google.com>2019-06-06 19:25:48 +0000
commita887c1b15b158321c48057387ff55645654cb97c (patch)
tree361025b99c4acf97caa7b870d9b0f122aa417e9e /src/soc/amd/stoneyridge/smbus.c
parente1780e9047ae12eae64df5ac3d2c19e5725e58b5 (diff)
src/amd/stoneyridge: Move alink source to common
Relocate the alink access functions out of stoneyridge where they were dead code. This source maintains the ability to access all register spaces, however more modern APUs define only ABCFG in the BKDGs. BUG=b:131682806 Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32663 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/smbus.c')
-rw-r--r--src/soc/amd/stoneyridge/smbus.c76
1 files changed, 0 insertions, 76 deletions
diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c
index df7a86edc7..31457f98b8 100644
--- a/src/soc/amd/stoneyridge/smbus.c
+++ b/src/soc/amd/stoneyridge/smbus.c
@@ -189,79 +189,3 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val)
return 0;
}
-
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
- u32 tmp;
-
- outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
- tmp = inl(AB_DATA);
- /* rpr 4.2
- * For certain revisions of the chip, the ABCFG registers,
- * with an address of 0x100NN (where 'N' is any hexadecimal
- * number), require an extra programming step.*/
- outl(0, AB_INDX);
-
- tmp &= ~mask;
- tmp |= val;
-
- // printk(BIOS_DEBUG, "about write %x, index=%x", tmp,
- // (reg_space&0x3)<<29 | reg_addr);
-
- /* probably we dont have to do it again. */
- outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
- outl(tmp, AB_DATA);
- outl(0, AB_INDX);
-}
-
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
-{
- u32 tmp;
-
- outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
- tmp = inl(AB_DATA);
- /* rpr 4.2
- * For certain revisions of the chip, the ABCFG registers,
- * with an address of 0x100NN (where 'N' is any hexadecimal
- * number), require an extra programming step.*/
- outl(0, AB_INDX);
-
- tmp &= ~mask;
- tmp |= val;
-
- //printk(BIOS_DEBUG, "about write %x, index=%x", tmp,
- // (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
-
- /* probably we dont have to do it again. */
- outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
- outl(tmp, AB_DATA);
- outl(0, AB_INDX);
-}
-
-/*
- * space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
-{
- u32 tmp;
-
- /* read axindc to tmp */
- outl(space << 29 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(0, AB_INDX);
- outl(space << 29 | space << 3 | 0x34, AB_INDX);
- tmp = inl(AB_DATA);
- outl(0, AB_INDX);
-
- tmp &= ~mask;
- tmp |= val;
-
- /* write tmp */
- outl(space << 29 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(0, AB_INDX);
- outl(space << 29 | space << 3 | 0x34, AB_INDX);
- outl(tmp, AB_DATA);
- outl(0, AB_INDX);
-}