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authorAaron Durbin <adurbin@chromium.org>2020-01-28 11:20:05 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-02-04 16:13:11 +0000
commit3d2e18ad50d6dd0e93af1bb6efad20b4faede3b3 (patch)
tree129878b66d7295fd8ef397e38b68c5df28f85ac3 /src/soc/amd/stoneyridge/smbus.c
parent16a23c0e101ae567b9b32aeb1d643f4b0a992cf0 (diff)
soc/amd: unify SMBus support
The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/smbus.c')
-rw-r--r--src/soc/amd/stoneyridge/smbus.c196
1 files changed, 0 insertions, 196 deletions
diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c
deleted file mode 100644
index 5474c5cd45..0000000000
--- a/src/soc/amd/stoneyridge/smbus.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <console/console.h>
-#include <device/smbus_host.h>
-#include <amdblocks/acpimmio.h>
-#include <soc/southbridge.h>
-
-/*
- * Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100 * 1000 * 10)
-
-static u8 controller_read8(uintptr_t base, u8 reg)
-{
- switch (base) {
- case ACPIMMIO_SMBUS_BASE:
- return smbus_read8(reg);
- case ACPIMMIO_ASF_BASE:
- return asf_read8(reg);
- default:
- printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n",
- base);
- }
- return 0xff;
-}
-
-static void controller_write8(uintptr_t base, u8 reg, u8 val)
-{
- switch (base) {
- case ACPIMMIO_SMBUS_BASE:
- smbus_write8(reg, val);
- break;
- case ACPIMMIO_ASF_BASE:
- asf_write8(reg, val);
- break;
- default:
- printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n",
- base);
- }
-}
-
-static int smbus_wait_until_ready(uintptr_t mmio)
-{
- u32 loops;
- loops = SMBUS_TIMEOUT;
- do {
- u8 val;
- val = controller_read8(mmio, SMBHSTSTAT);
- val &= SMBHST_STAT_VAL_BITS;
- if (val == 0) { /* ready now */
- return 0;
- }
- controller_write8(mmio, SMBHSTSTAT, val);
- } while (--loops);
- return -2; /* time out */
-}
-
-static int smbus_wait_until_done(uintptr_t mmio)
-{
- u32 loops;
- loops = SMBUS_TIMEOUT;
- do {
- u8 val;
-
- val = controller_read8(mmio, SMBHSTSTAT);
- val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */
- if (val & SMBHST_STAT_ERROR_BITS)
- return -5; /* error */
- if (val == SMBHST_STAT_NOERROR) {
- controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */
- return 0;
- }
- } while (--loops);
- return -3; /* timeout */
-}
-
-int do_smbus_recv_byte(uintptr_t mmio, u8 device)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(mmio) < 0)
- return -2; /* not ready */
-
- /* set the device I'm talking to */
- controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
-
- byte = controller_read8(mmio, SMBHSTCTRL);
- byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
- byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */
- controller_write8(mmio, SMBHSTCTRL, byte);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(mmio) < 0)
- return -3; /* timeout or error */
-
- /* read results of transaction */
- byte = controller_read8(mmio, SMBHSTDAT0);
-
- return byte;
-}
-
-int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(mmio) < 0)
- return -2; /* not ready */
-
- /* set the command... */
- controller_write8(mmio, SMBHSTDAT0, val);
-
- /* set the device I'm talking to */
- controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
-
- byte = controller_read8(mmio, SMBHSTCTRL);
- byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
- byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */
- controller_write8(mmio, SMBHSTCTRL, byte);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(mmio) < 0)
- return -3; /* timeout or error */
-
- return 0;
-}
-
-int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(mmio) < 0)
- return -2; /* not ready */
-
- /* set the command/address... */
- controller_write8(mmio, SMBHSTCMD, address & 0xff);
-
- /* set the device I'm talking to */
- controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
-
- byte = controller_read8(mmio, SMBHSTCTRL);
- byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
- byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */
- controller_write8(mmio, SMBHSTCTRL, byte);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(mmio) < 0)
- return -3; /* timeout or error */
-
- /* read results of transaction */
- byte = controller_read8(mmio, SMBHSTDAT0);
-
- return byte;
-}
-
-int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(mmio) < 0)
- return -2; /* not ready */
-
- /* set the command/address... */
- controller_write8(mmio, SMBHSTCMD, address & 0xff);
-
- /* set the device I'm talking to */
- controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
-
- /* output value */
- controller_write8(mmio, SMBHSTDAT0, val);
-
- byte = controller_read8(mmio, SMBHSTCTRL);
- byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
- byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */
- controller_write8(mmio, SMBHSTCTRL, byte);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(mmio) < 0)
- return -3; /* timeout or error */
-
- return 0;
-}