diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-06-15 12:17:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 20:50:54 +0000 |
| commit | 4e101ada37c10282030729f4a03fd505bd4f526d (patch) | |
| tree | 7cdb6f41b198ef1e9c30f66da854572893de91ed /src/soc/amd/stoneyridge/sd.c | |
| parent | 4692e2fc95605a997cd9cd1cdb711e6c1f6869bc (diff) | |
soc/amd/stoneyridge: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the
remaining ones as todo. (Some of the lines requiring a >80
break are indented too much currently.) Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.
Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia
build. No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().
BUG=chrome-os-partner:622407746
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/sd.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/sd.c | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/src/soc/amd/stoneyridge/sd.c b/src/soc/amd/stoneyridge/sd.c index 484dee4227..7188aad55f 100644 --- a/src/soc/amd/stoneyridge/sd.c +++ b/src/soc/amd/stoneyridge/sd.c @@ -25,27 +25,26 @@ static void sd_init(struct device *dev) { u32 stepping; - stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC); + stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), + 0xfc); struct soc_amd_stoneyridge_config *sd_chip = (struct soc_amd_stoneyridge_config *)(dev->chip_info); if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ - pci_write_config32(dev, 0xA4, 0x31FEC8B2); - pci_write_config32(dev, 0xA8, 0x00002503); - pci_write_config32(dev, 0xB0, 0x02180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); - } - else { /* SD 2.0 mode */ - if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */ - pci_write_config32(dev, 0xA4, 0x31DE32B2); - pci_write_config32(dev, 0xB0, 0x01180C19); - pci_write_config32(dev, 0xD0, 0x0000058B); - } - else { /* Stepping >= A1 */ - pci_write_config32(dev, 0xA4, 0x31FE3FB2); - pci_write_config32(dev, 0xB0, 0x01180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); + pci_write_config32(dev, 0xa4, 0x31fec8b2); + pci_write_config32(dev, 0xa8, 0x00002503); + pci_write_config32(dev, 0xb0, 0x02180c19); + pci_write_config32(dev, 0xd0, 0x0000078b); + } else { /* SD 2.0 mode */ + if ((stepping & 0x0000000f) == 0) { /* Stepping A0 */ + pci_write_config32(dev, 0xa4, 0x31de32b2); + pci_write_config32(dev, 0xb0, 0x01180c19); + pci_write_config32(dev, 0xd0, 0x0000058b); + } else { /* Stepping >= A1 */ + pci_write_config32(dev, 0xa4, 0x31fe3fb2); + pci_write_config32(dev, 0xb0, 0x01180c19); + pci_write_config32(dev, 0xd0, 0x0000078b); } } } |