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authorMarc Jones <marcj303@gmail.com>2018-02-08 23:19:29 -0700
committerMartin Roth <martinroth@google.com>2018-02-21 16:08:45 +0000
commitfa650f5e8c7cd81138b60d09d4a41b5454f03cc1 (patch)
tree5d1fdcbe556dcd663f65d03720228b7e79bde28e /src/soc/amd/stoneyridge/sb_util.c
parent950332b6e4c736bf948d2ebe8721bde568f5dfc0 (diff)
soc/amd/stoneyridge: Add UMA save function
Save the UMA values from AGESA to use in resource allocation in ramstage. Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23817 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/sb_util.c')
-rw-r--r--src/soc/amd/stoneyridge/sb_util.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index a98a334fe2..26c86e8238 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -164,3 +164,27 @@ int acpi_get_sleep_type(void)
{
return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk()));
}
+
+void save_uma_size(uint32_t size)
+{
+ biosram_write32(BIOSRAM_UMA_SIZE, size);
+}
+
+void save_uma_base(uint64_t base)
+{
+ biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base);
+ biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32));
+}
+
+uint32_t get_uma_size(void)
+{
+ return biosram_read32(BIOSRAM_UMA_SIZE);
+}
+
+uint64_t get_uma_base(void)
+{
+ uint64_t base;
+ base = biosram_read32(BIOSRAM_UMA_BASE);
+ base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32);
+ return base;
+}