amd/stoneyridge: Convert MP init to mp_init_with_smm

Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.

Add a new cpu.c file for most of the processor initiliazation.  Build
mp_ops with the necessary callbacks.  Note also that this patch removes
cpu_bus_scan.  Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.

SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time.  A later patch will add TSEG SMM
capabilities for the APU.

This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.

BUG=b:66200075

Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 37 insertions, 2 deletions

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index c69bbf6403..b062c6c4a9 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>
@@ -24,15 +27,47 @@
 
 asmlinkage void car_stage_entry(void)
 {
+	msr_t base, mask;
+	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+	int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
+	int i;
+
 	console_init();
 
 	post_code(0x40);
 	AGESAWRAPPER(amdinitpost);
 
 	post_code(0x41);
-	psp_notify_dram();
+	/*
+	 * TODO: This is a hack to work around current AGESA behavior.  AGESA
+	 *       needs to change to reflect that coreboot owns the MTRRs.
+	 *
+	 * After setting up DRAM, AGESA also completes the configuration of the
+	 * MTRRs, setting regions to WB.  Anything written to memory between
+	 * now and and when CAR is dismantled will be in cache and lost.  For
+	 * now, set the regions UC to ensure the writes get to DRAM.
+	 */
+	for (i = 0 ; i < vmtrrs ; i++) {
+		base = rdmsr(MTRR_PHYS_BASE(i));
+		mask = rdmsr(MTRR_PHYS_MASK(i));
+		if (!(mask.lo & MTRR_PHYS_MASK_VALID))
+			continue;
+
+		if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) {
+			base.lo &= ~0x7;
+			base.lo |= MTRR_TYPE_UNCACHEABLE;
+			wrmsr(MTRR_PHYS_BASE(i), base);
+		}
+	}
+	/* Disable WB from to region 4GB-TOM2. */
+	msr_t sys_cfg = rdmsr(SYSCFG_MSR);
+	sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
+	wrmsr(SYSCFG_MSR, sys_cfg);
 
 	post_code(0x42);
+	psp_notify_dram();
+
+	post_code(0x43);
 	cbmem_initialize_empty();
 
 	/*
@@ -42,7 +77,7 @@ asmlinkage void car_stage_entry(void)
 	 */
 	chipset_teardown_car();
 
-	post_code(0x43);
+	post_code(0x44);
 	AGESAWRAPPER(amdinitenv);
 
 	post_code(0x50);