amd/stoneyridge: Add warm reset detection

Extend the existing reset handling features in Stoney Ridge to plan for,
and recognize, warm resets.  The ColdRstDet bit is always zero on a cold
reset, and is intended as a mechanism for the BIOS to determine the type
of a reset that occurred.

Set ColdRstDet=1 after all cores have been initialized, so that any
subsequent reset may be identified as warm/cold.  A later patch will check
the value during mp_init.

Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
index a133a88b92..738ec59354 100644
--- a/src/soc/amd/stoneyridge/reset.c
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -21,6 +21,21 @@
 #include <device/pci_ops.h>
 #include <soc/southbridge.h>
 
+void set_warm_reset_flag(void)
+{
+	u32 htic;
+	htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
+	htic |= HTIC_COLD_RST_DET;
+	pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
+}
+
+int is_warm_reset(void)
+{
+	u32 htic;
+	htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
+	return !!(htic & HTIC_COLD_RST_DET);
+}
+
 /* Clear bits 5, 9 & 10, used to signal the reset type */
 static void clear_bios_reset(void)
 {
@@ -42,6 +57,7 @@ void do_hard_reset(void)
 
 void do_soft_reset(void)
 {
+	set_warm_reset_flag();
 	clear_bios_reset();
 
 	/* Assert reset signals only. */