amd/stoneyridge: Enable SMM in TSEG

Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.

SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size.  Add relocation attributes to be set by each
core a relocation handler.

Modify the definition of smi_southbridge_handler() to match TSEG
prototype.

BUG=b:62103112

Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 53 insertions, 2 deletions

diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index bdad8d6057..8268477a32 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -1,6 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Intel Corp.
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -13,11 +15,13 @@
 
 #define __SIMPLE_DEVICE__
 
+#include <assert.h>
 #include <stdint.h>
 #include <arch/io.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
+#include <soc/northbridge.h>
 
 #define CBMEM_TOP_SCRATCHPAD 0x78
 
@@ -41,7 +45,54 @@ void *cbmem_top(void)
 	if (!tom.lo)
 		return 0;
 	else
-		/* 16MB alignment to keep MTRR usage low */
+		/* 8MB alignment to keep MTRR usage low */
 		return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
-				- CONFIG_SMM_TSEG_SIZE, 16*MiB);
+				- CONFIG_SMM_TSEG_SIZE, 8*MiB);
+}
+
+static uintptr_t smm_region_start(void)
+{
+	return (uintptr_t)cbmem_top();
+}
+
+static size_t smm_region_size(void)
+{
+	return CONFIG_SMM_TSEG_SIZE;
+}
+
+void smm_region_info(void **start, size_t *size)
+{
+	*start = (void *)smm_region_start();
+	*size = smm_region_size();
+}
+
+int smm_subregion(int sub, void **start, size_t *size)
+{
+	uintptr_t sub_base;
+	size_t sub_size;
+	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+	sub_base = smm_region_start();
+	sub_size = smm_region_size();
+
+	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+
+	switch (sub) {
+	case SMM_SUBREGION_HANDLER:
+		/* Handler starts at the base of TSEG. */
+		sub_size -= cache_size;
+		break;
+	case SMM_SUBREGION_CACHE:
+		/* External cache is in the middle of TSEG. */
+		sub_base += sub_size - cache_size;
+		sub_size = cache_size;
+		break;
+	default:
+		return -1;
+	}
+
+	*start = (void *)sub_base;
+	*size = sub_size;
+
+	return 0;
 }