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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2017-09-23 21:39:06 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-27 16:39:03 +0000 |
| commit | 5a01d6a152d705ded302e92c4438d8b8dc495465 (patch) | |
| tree | 139cab8918f8e2503d30c22c26b841d83c31c242 /src/soc/amd/stoneyridge/ramtop.c | |
| parent | 7090377a873aaef9715b9ac8e669e9ca1a3b3651 (diff) | |
arch/riscv: trap handler: Print load/store access width in bits
This is easier to read than the raw shift amount that's extracted from
load/store instructions.
Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/ramtop.c')
0 files changed, 0 insertions, 0 deletions