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| author | Jonathon Hall <jonathon.hall@puri.sm> | 2023-08-29 13:30:09 -0400 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-12-02 01:03:48 +0000 |
| commit | 5c766bc150f7ab6829f968b1ea0ddf7890a3b5f5 (patch) | |
| tree | 41daef8a66159f6a86cdf1f344111e954c430de1 /src/soc/amd/stoneyridge/pcie.c | |
| parent | 2007792b0833eaefd5c72a3730d0e0ef1d673ad2 (diff) | |
mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
Since commit e633d370 (soc/intel/cometlake: Enable early caching of
RAMTOP region), cmos.layout for Cannon Lake boards must have a ramtop
entry, add it.
Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77670
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/pcie.c')
0 files changed, 0 insertions, 0 deletions