amd/stoneyridge: Convert MP init to mp_init_with_smm

Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.

Add a new cpu.c file for most of the processor initiliazation.  Build
mp_ops with the necessary callbacks.  Note also that this patch removes
cpu_bus_scan.  Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.

SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time.  A later patch will add TSEG SMM
capabilities for the APU.

This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.

BUG=b:66200075

Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 0 insertions, 74 deletions

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 049bcd0674..11fb336058 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -507,80 +507,6 @@ void domain_set_resources(device_t dev)
 	reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);
 }
 
-void cpu_bus_scan(device_t dev)
-{
-	struct bus *cpu_bus;
-	device_t cpu;
-	device_t cdb_dev;
-	device_t dev_mc;
-	int j;
-	int core_max;
-	int core_nums;
-	int siblings;
-	int family;
-	int enable_node;
-	u32 lapicid_start;
-	u32 apic_id;
-	u32 pccount;
-
-
-	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
-	if (!dev_mc) {
-		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB,
-				CONFIG_CDB);
-		die("");
-	}
-
-	/* Get max and actual number of cores */
-	pccount = cpuid_ecx(0x80000008);
-	core_max = 1 << ((pccount >> 12) & 0xf);
-	core_nums = (pccount & 0xF);
-
-	family = (cpuid_eax(1) >> 20) & 0xff;
-
-	cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5));
-	siblings = pci_read_config32(cdb_dev, 0x84) & 0xff;
-
-	printk(BIOS_SPEW, "%s family%xh, core_max=%d, core_nums=%d,"
-			" siblings=%d\n", dev_path(cdb_dev), 0x0f + family,
-			core_max, core_nums, siblings);
-
-	/*
-	 * APIC ID calucation is tightly coupled with AGESA v5 code.
-	 * This calculation MUST match the assignment calculation done
-	 * in LocalApicInitializationAtEarly() function.
-	 * And reference GetLocalApicIdForCore()
-	 *
-	 * Apply apic enumeration rules
-	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
-	 * put the local-APICs at m..z
-	 *
-	 * This is needed because many IO-APIC devices only have 4 bits
-	 * for their APIC id and therefore must reside at 0..15
-	 */
-
-	 /*
-	  * While the above statement is true, we know some things about
-	  * this silicon. It is an SOC and can't have  >= 16 APICs, but
-	  * we will start numbering at 0x10. We also know there is only
-	  * on physical node (module in AMD speak).
-	  */
-
-	lapicid_start = 0x10; /* Get this from devicetree? see comment above. */
-	enable_node = cdb_dev->enabled;
-	cpu_bus = dev->link_list;
-
-	for (j = 0 ; j <= siblings ; j++) {
-		apic_id = lapicid_start + j;
-		printk(BIOS_SPEW, "lapicid_start 0x%x, core 0x%x,"
-				"  apicid=0x%x\n", lapicid_start, j, apic_id);
-
-		cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
-		if (cpu)
-			amd_cpu_topology(cpu, 1, j);
-	}
-}
-
 /*********************************************************************
  * Change the vendor / device IDs to match the generic VBIOS header. *
  *********************************************************************/