diff options
| author | Chris Ching <chingcodes@google.com> | 2017-10-19 11:45:30 -0600 |
|---|---|---|
| committer | Chris Ching <chingcodes@chromium.org> | 2017-10-19 21:07:10 +0000 |
| commit | 6a35fab2723f3b1ca288cd9224d263570cfbe184 (patch) | |
| tree | 5b07742b8fe915db4d1fddc1af320a670f7ba699 /src/soc/amd/stoneyridge/northbridge.c | |
| parent | c5ecd3e14d17c5634247242afc8cd558c1ae158f (diff) | |
soc/amd/stoneyridge: Use macros for PCI_DEVFN calls
* Change all calls to PCI_DEVFN to macros
* Remove CBB and CDB Kconfig since these are static for stoneyridge
BUG=b:62200746
TEST=build
Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/northbridge.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4d44a49564..39001af58f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -338,12 +338,12 @@ void fam15_finalize(void *chip_info) { device_t dev; u32 value; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xf8, 0); pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */ /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + dev = dev_find_slot(0, HDA0_DEVFN); value = pci_read_config32(dev, 0x60); value &= ~(1 << 11); pci_write_config32(dev, 0x60, value); |