diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-12 22:10:24 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-14 02:22:59 +0000 |
| commit | 2d0346a52126326bf888a9a3d778dc38515d2235 (patch) | |
| tree | 2ab8d9f7d7793e6537babcdffecaf4f417c4213e /src/soc/amd/stoneyridge/mca.c | |
| parent | 82af7491c267bfd74c6c3c4f63fe091b10814fb1 (diff) | |
soc/amd/picasso,stoneyridge/mca: factor out mca_print_error()
Change-Id: I7cd05a389c34c2e5f3d0ab4cd06d60a7e3e5cad9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56239
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/mca.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/mca.c | 41 |
1 files changed, 22 insertions, 19 deletions
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 942508918e..06b35bbf95 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -145,6 +145,25 @@ static const char *const mca_bank_name[] = { "Floating point unit" }; +static void mca_print_error(unsigned int bank) +{ + msr_t msr; + + printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, + mca_bank_name[bank]); + + msr = rdmsr(IA32_MC0_STATUS + (bank * 4)); + printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_ADDR + (bank * 4)); + printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_MISC + (bank * 4)); + printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_CTL + (bank * 4)); + printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MC0_CTL_MASK + bank); + printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); +} + void check_mca(void) { unsigned int i; @@ -157,27 +176,11 @@ void check_mca(void) if (i == 3) /* Reserved in Family 15h */ continue; + mci.bank = i; mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { - printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", - initial_lapicid(), i, mca_bank_name[i]); - - printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", - i, mci.sts.hi, mci.sts.lo); - msr = rdmsr(IA32_MC0_ADDR + (i * 4)); - printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_MISC + (i * 4)); - printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_CTL + (i * 4)); - printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + i); - printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", - i, msr.hi, msr.lo); - - mci.bank = i; + mca_print_error(i); + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } |