diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/soc/amd/stoneyridge/mca.c | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/mca.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/mca.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index df2b9611bf..13e626e397 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -133,11 +133,11 @@ static void build_bert_mca_error(struct mca_bank *mci) if (!chk) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCG_CAP, 3); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, - MC0_CTL + (mci->bank * 4), 4); + IA32_MC0_CTL + (mci->bank * 4), 4); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, @@ -169,7 +169,7 @@ void check_mca(void) struct mca_bank mci; int num_banks; - cap = rdmsr(MCG_CAP); + cap = rdmsr(IA32_MCG_CAP); num_banks = cap.lo & MCA_BANKS_MASK; if (is_warm_reset()) { @@ -177,7 +177,7 @@ void check_mca(void) if (i == 3) /* Reserved in Family 15h */ continue; - mci.sts = rdmsr(MC0_STATUS + (i * 4)); + mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; @@ -192,7 +192,7 @@ void check_mca(void) mci.misc = rdmsr(MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(MC0_CTL + (i * 4)); + mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", i, mci.ctl.hi, mci.ctl.lo); mci.cmask = rdmsr(MC0_CTL_MASK + i); @@ -211,5 +211,5 @@ void check_mca(void) mci.sts.lo = 0; mci.sts.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(MC0_STATUS + (i * 4), mci.sts); + wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); } |