diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-10-22 13:57:18 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-30 16:57:53 +0000 |
| commit | 41baf0c3ff8bf23a154eb6505c4e254f5bdc253b (patch) | |
| tree | e643d364058d032964026e60f01eda512bbd4f6b /src/soc/amd/stoneyridge/lpc.c | |
| parent | 58bf3e763297d658ed83dd35b30293dfab3e135f (diff) | |
soc/amd/stoneyridge: Remove dev_find_slot where possible
The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.
BUG=b:117917136
TEST=Build grunt.
Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/lpc.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/lpc.c | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 6833db6a8a..317574b36c 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -38,32 +38,30 @@ static void lpc_init(struct device *dev) { u8 byte; u32 dword; - struct device *sm_dev; /* * Enable the LPC Controller * SMBus register 0x64 is not defined in public datasheet. */ - sm_dev = dev_find_slot(0, SMBUS_DEVFN); - dword = pci_read_config32(sm_dev, 0x64); + dword = pci_read_config32(SOC_SMBUS_DEV, 0x64); dword |= 1 << 20; - pci_write_config32(sm_dev, 0x64, dword); + pci_write_config32(SOC_SMBUS_DEV, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(dev, LPC_PCI_CONTROL); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL); byte |= LEGACY_DMA_EN; - pci_write_config8(dev, LPC_PCI_CONTROL, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte); /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; - pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte); /* Disable LPC MSI Capability */ - byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS); /* BIT 1 is not defined in public datasheet. */ byte &= ~(1 << 1); @@ -73,15 +71,15 @@ static void lpc_init(struct device *dev) * interrupt and visit LPC. */ byte &= ~LPC_NOHOG; - pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte); /* * Enable hand-instance of the pulse generator and SPI * controller prefetch of flash. */ - byte = pci_read_config8(dev, LPC_HOST_CONTROL); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL); byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; - pci_write_config8(dev, LPC_HOST_CONTROL, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte); cmos_check_update_date(); |