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authorGarrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>2018-03-07 16:12:11 -0600
committerPatrick Georgi <pgeorgi@google.com>2018-03-14 11:17:11 +0000
commit6575306663987225080abbe3d5b1e70ba5302e84 (patch)
tree427cbed31a5b774780c4ec8cee2b464254f2775f /src/soc/amd/stoneyridge/include
parentbe33a674bb5d7081d77077d9d486bcc45b2624cd (diff)
soc/amd/stoneyridge: Configure FCH for TPM
In preparation for moving AGESA calls out of the bootblock: * Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy TPM IO 0x7f-0x7e and 0xef-0xee * Modify sb_tpm_decode_spi to additionally call sb_tpm_decode. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt (with other changes to call code not committed at this time) Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index cccdf9736f..434877e15e 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -186,6 +186,10 @@
#define LPC_MISC_CONTROL_BITS 0x78
#define LPC_NOHOG BIT(0)
+#define LPC_TRUSTED_PLATFORM_MODULE 0x7c
+#define TPM_12_EN BIT(0)
+#define TPM_LEGACY_EN BIT(2)
+
#define LPC_WIDEIO2_GENERIC_PORT 0x90
/*
@@ -357,6 +361,7 @@ void sb_pci_port80(void);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
void sb_set_readspeed(u16 norm, u16 fast);
+void sb_tpm_decode(void);
void sb_tpm_decode_spi(void);
void lpc_wideio_512_window(uint16_t base);
void lpc_wideio_16_window(uint16_t base);