aboutsummaryrefslogtreecommitdiff
path: root/src/soc/amd/stoneyridge/include
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2021-01-29 16:01:10 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-30 17:17:48 +0000
commita21690ba1276f94365a685fa04901e0273c426bd (patch)
treebd818b575eb51f9b03e47e487c57e62999cb6cc4 /src/soc/amd/stoneyridge/include
parentffc87e9cbe1a811332de6a87186e9c3ad3755709 (diff)
soc/amd/stoneyridge/southbridge: replace southbridge prefix with fch
This aligns the function names with Picasso and Cezanne. Also move the fch_* functions in the header file in the order they get called. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49db8021edae5e537f043bf52eea1be54dc46eca Reviewed-on: https://review.coreboot.org/c/coreboot/+/50124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index f963fdfe84..72cc60a165 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -233,15 +233,16 @@ typedef struct aoac_devs {
#define XHCI_FW_SIZE_OFFSET 0x8
#define XHCI_FW_BOOTRAM_SIZE 0x8000
+void bootblock_fch_early_init(void);
+void bootblock_fch_init(void);
+void fch_init(void *chip_info);
+void fch_final(void *chip_info);
+
void enable_aoac_devices(void);
void sb_clk_output_48Mhz(u32 osc);
void sb_enable(struct device *dev);
-void southbridge_final(void *chip_info);
-void southbridge_init(void *chip_info);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
-void bootblock_fch_early_init(void);
-void bootblock_fch_init(void);
/*
* Call the mainboard to get the USB Over Current Map. The mainboard