diff options
| author | Martin Roth <martinroth@google.com> | 2017-11-12 14:54:09 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-01 03:29:22 +0000 |
| commit | 48e44eecc75c71118214a9192f347d256f98da35 (patch) | |
| tree | 6ba4e1f8d8359f4d4aa75dd8be0ca43415129bb9 /src/soc/amd/stoneyridge/include | |
| parent | 88a61bbd00ea2da6c0c0f40219783b207b72643e (diff) | |
soc/amd/stoney: clean up and update reset.c
- Move #defines to soc/northbridge.h, add other reset definitions to
soc/southbridge.h.
- Clean up file to use definitions instead of magic numbers.
- Add do_soft_reset()
BUG=b:69224851
TEST=Build gardenia; Build & boot Kahlee
Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22439
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/northbridge.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 9 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 0cf94289bb..b0bbd5497e 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -24,6 +24,8 @@ #define D18F0_NODE_ID 0x60 #define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */ # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ +#define HT_INIT_CONTROL 0x6c +# define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10)) /* D18F1 - Address Map Registers */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 238feba53a..d9114728e3 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -259,6 +259,15 @@ #define FCH_MISC_REG40_OSCOUT1_EN BIT(2) +/* IO 0xcf9 - Reset control port*/ +#define FULL_RST BIT(3) +#define RST_CMD BIT(2) +#define SYS_RST BIT(1) + +/* PMx10 - Power Reset Config */ +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD BIT(1) + static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ |