soc/amd/stoneyridge: Add GNVS

Add ACPI asl for global non-volatile storage (GNVS).

Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 89 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
new file mode 100644
index 0000000000..f573b0ed81
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_STONEYRIDGE_ACPI_H_
+#define _SOC_STONEYRIDGE_ACPI_H_
+
+#include <arch/acpi.h>
+
+#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)
+	#define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
+#else
+	#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
+#endif
+
+#ifndef FADT_PM_PROFILE
+	#define FADT_PM_PROFILE PM_UNSPECIFIED
+#endif
+
+unsigned long southbridge_write_acpi_tables(device_t device,
+		unsigned long current, struct acpi_rsdp *rsdp);
+
+void southbridge_inject_dsdt(device_t device);
+
+#endif	/* _SOC_STONEYRIDGE_ACPI_H_ */
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
new file mode 100644
index 0000000000..b28f386ec8
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * in soc/soc/amd/stoneyridge/acpi/globalnvs.asl !!!
+ *
+ */
+
+#ifndef _SOC_STONEYRIDGE_NVS_H_
+#define _SOC_STONEYRIDGE_NVS_H_
+
+#include <stdint.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+typedef struct global_nvs_t {
+	/* Miscellaneous */
+	uint8_t		pcnt; /* 0x00 - Processor Count */
+	uint8_t		ppcm; /* 0x01 - Max PPC State */
+	uint8_t		lids; /* 0x02 - LID State */
+	uint8_t		pwrs; /* 0x03 - AC Power State */
+	uint8_t		dpte; /* 0x04 - Enable DPTF */
+	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
+	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */
+	uint32_t	nhll; /* 0x21 - 0x24 - NHLT Length */
+	uint32_t	prt0; /* 0x25 - 0x28 - PERST_0 Address */
+	uint8_t		scdp; /* 0x29 - SD_CD GPIO portid */
+	uint8_t		scdo; /* 0x2A - GPIO pad offset relative to the community */
+	uint8_t		unused[213];
+
+	/* ChromeOS specific (0x100 - 0xfff) */
+	chromeos_acpi_t chromeos;
+} __attribute__((packed)) global_nvs_t;
+
+#endif	/* _SOC_STONEYRIDGE_NVS_H_ */