diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2018-01-26 16:39:04 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-01-30 05:38:08 +0000 |
| commit | 0d2d77a597542354a1fe64cad908f6a9e0d59591 (patch) | |
| tree | d890fa42eec3b94bea642c9bc718e0ac85be8545 /src/soc/amd/stoneyridge/include | |
| parent | 063c00c2e00b3457ac336763989a4b254345fb13 (diff) | |
soc/amd/stoneyridge: use new host controller programming
The SPI controller on stoneyridge apparently has a large fifo
and an alternate method for programming the controller. The
fifo is directly accessible as well as the rx and tx pointer
in addition to the execute bit. Remove the unneeded #defines
and program the host controller with the above changes in mind.
In addition, add debug hooks to the driver so one can dump the
state of the controller when in operation.
The time it took to read 4KiB of flash in the elog driver went
from 20593 microseconds to 5693 microseconds on cdx03/kahlee.
BUG=b:65485690
Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23493
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 33 |
1 files changed, 14 insertions, 19 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f77640e70d..fa427eedc1 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -193,8 +193,6 @@ #define SPI_FROM_HOST_PREFETCH_EN BIT(0) /* SPI Controller */ -#define SPI_FIFO_DEPTH 8 - #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) @@ -209,13 +207,21 @@ #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_REG_CNTRL01 0x01 -#define SPI_REG_CNTRL02 0x02 -#define SPI_FIFO_PTR_CLR02 (SPI_FIFO_PTR_CLR >> 16) #define SPI_CNTRL1 0x0c -#define SPI_FIFO_PTR_MASK (BIT(8) | BIT(9) | BIT(10)) -#define SPI_CNTRL11 0x0d -#define SPI_FIFO_PTR_MASK11 (SPI_FIFO_PTR_MASK >> 8) +#define SPI_CMD_CODE 0x45 +#define SPI_CMD_TRIGGER 0x47 +#define SPI_CMD_TRIGGER_EXECUTE (BIT(7)) +#define SPI_TX_BYTE_COUNT 0x48 +#define SPI_RX_BYTE_COUNT 0x4B +#define SPI_STATUS 0x4c +#define SPI_DONE_BYTE_COUNT_SHIFT 0 +#define SPI_DONE_BYTE_COUNT_MASK 0xff +#define SPI_FIFO_WR_PTR_SHIFT 8 +#define SPI_FIFO_WR_PTR_MASK 0x7f +#define SPI_FIFO_RD_PTR_SHIFT 16 +#define SPI_FIFO_RD_PTR_MASK 0x7f +#define SPI_FIFO 0x80 +#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) #define SPI100_SPEED_CONFIG 0x22 /* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ @@ -223,17 +229,6 @@ #define SPI_NORM_SPEED_SH 12 #define SPI_FAST_SPEED_SH 8 -#define SPI_EXT_INDEX 0x1e -#define SPI_EXT_DATA 0x1f -#define SPI_DDR_CMD 0x0 -#define SPI_QDR_CMD 0x1 -#define SPI_DPR_CMD 0x2 -#define SPI_QPR_CMD 0x3 -#define SPI_MODE_BYTE 0x4 -#define SPI_TX_BYTE_COUNT 0x5 -#define SPI_RX_BYTE_COUNT 0x6 -#define SPI_SPI_DATA_FIFO_PTR 0x7 - #define SPI100_ENABLE 0x20 #define SPI_USE_SPI100 BIT(0) |