diff options
| author | Edward Hill <ecgh@chromium.org> | 2018-08-10 16:20:02 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-16 16:30:52 +0000 |
| commit | cc68034ee9dfafab9ce2ac90d53299559a306980 (patch) | |
| tree | 3034533b8ab213d4916bd076c0d3953f405c2256 /src/soc/amd/stoneyridge/include | |
| parent | f716f2ac1a5e461b49b3d26d8727944ea825db17 (diff) | |
amd/stoneyridge: Add PMxC0 reset status to boot log
Print the PMxC0 S5/Reset status bits to the console.
TEST=Inspect console for Grunt
BUG=b:110788201
Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/28020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index c6f77916d8..530b93a3e4 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -91,6 +91,7 @@ #define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) +#define PM_RST_STATUS 0xc0 #define PM_PMIO_DEBUG 0xd2 #define PM_MANUAL_RESET 0xd3 #define PM_HUD_SD_FLASH_CTRL 0xe7 |