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authorFelix Held <felix-coreboot@felixheld.de>2021-02-09 16:47:09 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-11 00:46:12 +0000
commita8d4a718e3a95dde5146e67790e15ca3f3b71cf7 (patch)
treee952255ae27c2eb12947a131953195e07277d5f1 /src/soc/amd/stoneyridge/include
parente094b1f137fa6d3168b836c498ede87079a10b8e (diff)
soc/amd/stoneyridge: drop empty sb_enable
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 219af8437a..9480e8b713 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -238,7 +238,6 @@ void fch_final(void *chip_info);
void enable_aoac_devices(void);
void sb_clk_output_48Mhz(u32 osc);
-void sb_enable(struct device *dev);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);