diff options
| author | Richard Spiegel <richard.spiegel@silverbackltd.com> | 2017-12-01 08:24:26 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-07 02:31:45 +0000 |
| commit | 376dc82dca8be3c1cec3e317d2d175efa690d436 (patch) | |
| tree | 5a048bf9cbff4434feaad8a4059c19a5d713aa35 /src/soc/amd/stoneyridge/include | |
| parent | 8fdbd114ec528ac414b49393f6e856cee4056d87 (diff) | |
amd/stoneyridge: Create new name/IRQ association
Table intr_types[] is hard to maintain, and has unused spaces filled with
NULL. A new table format is needed that creates strong association between
the APIC register index and the associated IRQ name, is easy to maintain
and has no unused space (index) to indicate that a particular register is
unused while still indicating which registers are valid.
Also, the string that defines the name of associated IRQ should be declared
with "#define" in a header, but must be physically initiated in a source
file. The "#define" must make a strong association between the used register
index and the associated IRQ name. Example:
#define INDEX_0X16_NAME "PerMon\t"
BUG=b:69868534
TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh
Processors definitions for Pci_Intr_Index. Also, check for new output
format to confirm write_pci_int_table() is working as desired. There's
no test for write_pci_cfg_irqs, as it's not being used by kahlee.
Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index a8e75f6327..e160c89283 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,9 +18,8 @@ #define __AMD_PCI_INT_DEFS_H__ /* - * PIRQ and device routing - these define the index - * into the FCH PCI_INTR 0xC00/0xC01 interrupt - * routing table + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. */ #define PIRQ_NC 0x1f /* Not Used */ @@ -44,26 +44,18 @@ #define PIRQ_ASF 0x12 /* ASF */ #define PIRQ_HDA 0x13 /* HDA 14h.2 */ #define PIRQ_FC 0x14 /* FC */ -#define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ #define PIRQ_SD 0x17 /* SD */ +#define PIRQ_SDIO 0x1a /* SDIO */ #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ #define PIRQ_IMC3 0x23 /* IMC INT3 */ #define PIRQ_IMC4 0x24 /* IMC INT4 */ #define PIRQ_IMC5 0x25 /* IMC INT5 */ -#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ -#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ -#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ -#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ -#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ -#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ -#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ -#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */ +#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ - -#define FCH_INT_TABLE_SIZE 0x76 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #define PIRQ_I2C0 0x70 #define PIRQ_I2C1 0x71 |