diff options
| author | Justin TerAvest <teravest@chromium.org> | 2018-02-20 14:24:36 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-22 16:27:36 +0000 |
| commit | 36b568ce7c7fa7bfc32382fb968a72cf02313404 (patch) | |
| tree | 1e63b278aa263790bc5c5eea1001654f47a49dce /src/soc/amd/stoneyridge/include | |
| parent | 2e81f394cffc6f1993a5f004356ed35f6064fe48 (diff) | |
mb/google/kahlee: Correct bad gpio entry
There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.
BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.
Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
0 files changed, 0 insertions, 0 deletions