diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-28 17:32:30 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-02 22:27:38 +0000 |
| commit | eecb794c96f738d20bf4d5890bbad8b3834c9685 (patch) | |
| tree | a0be7275f8aad034afe4654f652f093b5b79d7ab /src/soc/amd/stoneyridge/include | |
| parent | 16745e39b636ad58e0f43b254ceb7812b7fbe7f9 (diff) | |
amd/stoneyridge: Move pm/smi_read/write functions to util file
Pull all pm_read and write, smi_read and write variants into a single
file.
Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/smi.h | 23 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 11 |
2 files changed, 7 insertions, 27 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index d4bd57077a..87d1a0a03a 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -20,9 +20,6 @@ #include <arch/io.h> -/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */ -#define SMI_BASE 0xfed80200 - #define SMI_SCI_STATUS 0x10 /* SMI source and status */ @@ -197,26 +194,6 @@ enum smi_lvl { SMI_LVL_HIGH = 1, }; -static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(SMI_BASE + offset), value); -} - void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void disable_gevent_smi(uint8_t gevent); void enable_acpi_cmd_smi(void); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 7393abcad5..80fcf87558 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -25,10 +25,9 @@ #define IO_APIC2_ADDR 0xfec20000 -/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ +/* Offsets from ACPI_MMIO_BASE */ +#define APU_SMI_BASE 0xfed80200 + #define PM_MMIO_BASE 0xfed80300 #define APU_UART0_BASE 0xfedc6000 @@ -194,6 +193,10 @@ u32 pm_read32(u8 reg); void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); void pm_write32(u8 reg, u32 value); +u16 smi_read16(u8 reg); +u32 smi_read32(u8 reg); +void smi_write16(u8 reg, u16 value); +void smi_write32(u8 reg, u32 value); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); |