diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-04 19:21:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-08-11 17:38:36 +0000 |
| commit | e0b0697fedf756a811d0326426ab36a59dd83161 (patch) | |
| tree | 96198304184b90b3f401f874314eea8fa0141c2b /src/soc/amd/stoneyridge/include | |
| parent | 6f426784606735beeeaabd2ce6d4d6236912c5fe (diff) | |
soc/amd/stoneyridge/acpi: clean up global NVS
Some fields in GNVS seem to be copied over from Apollolake to
Stoneyridge. This patch removes the unused fields.
Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/nvs.h | 42 |
1 files changed, 16 insertions, 26 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 864cfffa1a..9c479c6e62 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -17,32 +17,22 @@ struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ - uint8_t ppcm; /* 0x01 - Max PPC State */ - uint8_t lids; /* 0x02 - LID State */ - uint8_t pwrs; /* 0x03 - AC Power State */ - uint8_t dpte; /* 0x04 - Enable DPTF */ - uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ - uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ - uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ - uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ - uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ - uint8_t scdo; /* 0x2A - GPIO pad relative offset */ - uint8_t tmps; /* 0x2B - Temperature Sensor ID */ - uint8_t tlvl; /* 0x2C - Throttle Level Limit */ - uint8_t flvl; /* 0x2D - Current FAN Level */ - uint8_t tcrt; /* 0x2E - Critical Threshold */ - uint8_t tpsv; /* 0x2F - Passive Threshold */ - uint8_t tmax; /* 0x30 - CPU Tj_max */ - uint8_t pad1[3]; - aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ - uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ - uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ - uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ - uint32_t eh10; /* 0x40 - EHCI BAR */ - uint8_t unused[184]; + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ + uint8_t pad1[6]; + aoac_devs_t aoac; /* 0x20 - AOAC device enables */ + uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */ + uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */ + uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */ + uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */ + uint32_t eh10; /* 0x30 - EHCI BAR */ + uint8_t unused[204]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; |