soc/amd/stoneyridge: Add northbridge support

Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.

Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile

Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

2 files changed, 27 insertions, 1 deletions

diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 22c0fba123..07d4009efa 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -16,7 +16,7 @@
 #ifndef _STONEYRIDGE_GPIO_H_
 #define _STONEYRIDGE_GPIO_H_
 
-#include <soc/amd/common/amd_defs.h>
+#include <amd_defs.h>
 #include <types.h>
 
 #define CROS_GPIO_DEVICE_NAME	"AmdKern"
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
new file mode 100644
index 0000000000..9ecbb13a9a
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H
+#define NORTHBRIDGE_AMD_AGESA_FAM15H_H
+
+void cpu_bus_scan(device_t dev);
+void domain_enable_resources(device_t dev);
+void domain_read_resources(device_t dev);
+void domain_set_resources(device_t dev);
+void fam15_finalize(void *chip_info);
+void setup_uma_memory(void);
+
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */