soc: Add AMD Stoney Ridge southbridge code

Copy the Hudson/Kern code from southbridge/amd/pi/hudson.  This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/

Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops

Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
new file mode 100644
index 0000000000..30ab0d4839
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AMD_PCI_INT_TYPES_H
+#define AMD_PCI_INT_TYPES_H
+
+const char * intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
+	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",
+	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
+	[0x7F] = "RSVD\t",
+	[0x40] = "IDE\t", "SATA\t",
+	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
+	[0x62] = "GPIO\t",
+	[0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",
+};
+
+#endif /* AMD_PCI_INT_TYPES_H */