soc/amd/common: Introduce I2C driver common to all AMD SoCs

I2C driver is replicated in each generation of AMD SoCs. Introduce a
common I2C driver that can be used across all the AMD SoCs. To begin
with, peripheral reset functionality is moved into this common driver.
SoC specific I2C driver passes the SCL pin configuration in order for
the common driver to reset the peripherals. More functionality can be
moved here in subsequent changes.

Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as
an effort towards using inclusive language.

BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz.
localhost ~ # i2cdetect -y 0
Warning: Can't use SMBus Quick Write command, will skip some addresses
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- --
60:
70:
localhost ~ # i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:

Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 1 insertions, 90 deletions

diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
index 295a833046..7b0bc77e59 100644
--- a/src/soc/amd/stoneyridge/i2c.c
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -7,6 +7,7 @@
 #include <device/device.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/i2c.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
@@ -115,93 +116,3 @@ struct device_operations stoneyridge_i2c_mmio_ops = {
 	.acpi_name = i2c_acpi_name,
 	.acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt,
 };
-
-/*
- * I2C pins are open drain with external pull up, so in order to bit bang them
- * all, SCL pins must become GPIO inputs with no pull, then they need to be
- * toggled between input-no-pull and output-low. This table is for the initial
- * conversion of all SCL pins to input with no pull.
- */
-static const struct soc_amd_gpio i2c_2_gpi[] = {
-	PAD_GPI(I2C0_SCL_PIN, PULL_NONE),
-	PAD_GPI(I2C1_SCL_PIN, PULL_NONE),
-	PAD_GPI(I2C2_SCL_PIN, PULL_NONE),
-	PAD_GPI(I2C3_SCL_PIN, PULL_NONE),
-};
-#define saved_pins_count ARRAY_SIZE(i2c_2_gpi)
-
-/*
- * To program I2C pins without destroying their programming, the registers
- * that will be changed need to be saved first.
- */
-static void save_i2c_pin_registers(uint8_t gpio,
-					struct soc_amd_i2c_save *save_table)
-{
-	save_table->mux_value = iomux_read8(gpio);
-	save_table->control_value = gpio_read32(gpio);
-}
-
-static void restore_i2c_pin_registers(uint8_t gpio,
-					struct soc_amd_i2c_save *save_table)
-{
-	/* Write and flush posted writes. */
-	iomux_write8(gpio, save_table->mux_value);
-	iomux_read8(gpio);
-	gpio_write32(gpio, save_table->control_value);
-	gpio_read32(gpio);
-}
-
-/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
-void sb_reset_i2c_slaves(void)
-{
-	const struct soc_amd_stoneyridge_config *cfg;
-	const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
-	struct soc_amd_i2c_save save_table[saved_pins_count];
-	uint8_t i, j, control;
-
-	if (!dev || !dev->chip_info)
-		return;
-	cfg = dev->chip_info;
-	control = cfg->i2c_scl_reset & GPIO_I2C_MASK;
-	if (control == 0)
-		return;
-
-	/* Save and reprogram I2C SCL pins */
-	for (i = 0; i < saved_pins_count; i++)
-		save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
-	program_gpios(i2c_2_gpi, saved_pins_count);
-
-	/*
-	 * Toggle SCL back and forth 9 times under 100KHz. A single read is
-	 * needed after the writes to force the posted write to complete.
-	 */
-	for (j = 0; j < 9; j++) {
-		if (control & GPIO_I2C0_SCL)
-			gpio_write32(I2C0_SCL_PIN, GPIO_OUTPUT_ENABLE);
-		if (control & GPIO_I2C1_SCL)
-			gpio_write32(I2C1_SCL_PIN, GPIO_OUTPUT_ENABLE);
-		if (control & GPIO_I2C2_SCL)
-			gpio_write32(I2C2_SCL_PIN, GPIO_OUTPUT_ENABLE);
-		if (control & GPIO_I2C3_SCL)
-			gpio_write32(I2C3_SCL_PIN, GPIO_OUTPUT_ENABLE);
-
-		gpio_read32(0); /* Flush posted write */
-		udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
-
-		if (control & GPIO_I2C0_SCL)
-			gpio_write32(I2C0_SCL_PIN, 0);
-		if (control & GPIO_I2C1_SCL)
-			gpio_write32(I2C1_SCL_PIN, 0);
-		if (control & GPIO_I2C2_SCL)
-			gpio_write32(I2C2_SCL_PIN, 0);
-		if (control & GPIO_I2C3_SCL)
-			gpio_write32(I2C3_SCL_PIN, 0);
-
-		gpio_read32(0); /* Flush posted write */
-		udelay(4);
-	}
-
-	/* Restore I2C pins. */
-	for (i = 0; i < saved_pins_count; i++)
-		restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
-}