soc/amd/stoneyridge/gpio.c: Create I2C slave reset code

AMD's SOC do not wait for I2C transactions to complete before executing
a reset. Because of this, it's possible for the reset to happen in the
middle of a transaction, resulting on a slave hang. There are 2 possible
solutions:
If the slave has a reset pin connected to a GPIO pin, it can be used to
reset the slave, else the only solution is to bang SCL 9 times. Create
code that makes it easy to implement SCL bang, using a devicetree
register to define which I2C SCL lines needs to be reset.

BUG=b:114479395
TEST=Build and boot grunt. Look at transactions on a scope.

Change-Id: I7f74b7e45c509044825355874753969f074e2382
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28574
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 102 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index b469f820b2..cc54f2c82d 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -17,8 +17,10 @@
 
 #include <arch/io.h>
 #include <console/console.h>
+#include <delay.h>
 #include <gpio.h>
 #include <soc/gpio.h>
+#include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <assert.h>
 
@@ -237,6 +239,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 
 		mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
 		write8(mux_ptr, mux & AMD_GPIO_MUX_MASK);
+		read8(mux_ptr); /* Flush posted write */
 		/* special case if pin 2 is assigned to wake */
 		if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK))
 			route_sci(GPIO_2_EVENT);
@@ -296,6 +299,105 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 					edge_level, mask);
 }
 
+/*
+ * I2C pins are open drain with external pull up, so in order to bit bang them
+ * all, SCL pins must become GPIO inputs with no pull, then they need to be
+ * toggled between input-no-pull and output-low. This table is for the initial
+ * conversion of all SCL pins to input with no pull.
+ */
+static const struct soc_amd_gpio i2c_2_gpi[] = {
+	PAD_GPI(I2C0_SCL_PIN, PULL_NONE),
+	PAD_GPI(I2C1_SCL_PIN, PULL_NONE),
+	PAD_GPI(I2C2_SCL_PIN, PULL_NONE),
+	PAD_GPI(I2C3_SCL_PIN, PULL_NONE),
+};
+#define saved_pins_count ARRAY_SIZE(i2c_2_gpi)
+
+/*
+ * To program I2C pins without destroying their programming, the registers
+ * that will be changed need to be saved first.
+ */
+static void save_i2c_pin_registers(uint8_t gpio,
+					struct soc_amd_i2c_save *save_table)
+{
+	uint32_t *gpio_ptr;
+	uint8_t *mux_ptr;
+
+	mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
+	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
+	save_table->mux_value = read8(mux_ptr);
+	save_table->control_value = read32(gpio_ptr);
+}
+
+static void restore_i2c_pin_registers(uint8_t gpio,
+					struct soc_amd_i2c_save *save_table)
+{
+	uint32_t *gpio_ptr;
+	uint8_t *mux_ptr;
+
+	mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
+	gpio_ptr = (uint32_t *)gpio_get_address(gpio);
+	write8(mux_ptr, save_table->mux_value);
+	read8(mux_ptr);
+	write32(gpio_ptr, save_table->control_value);
+	read32(gpio_ptr);
+}
+
+/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
+void sb_reset_i2c_slaves(void)
+{
+	const struct soc_amd_stoneyridge_config *cfg;
+	const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+	struct soc_amd_i2c_save save_table[saved_pins_count];
+	uint8_t i, j, control;
+
+	if (!dev || !dev->chip_info)
+		return;
+	cfg = dev->chip_info;
+	control = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+	if (control == 0)
+		return;
+
+	/* Save and reprogram I2C SCL pins */
+	for (i = 0; i < saved_pins_count; i++)
+		save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
+	sb_program_gpios(i2c_2_gpi, saved_pins_count);
+
+	/*
+	 * Toggle SCL back and forth 9 times under 100KHz. A single read is
+	 * needed after the writes to force the posted write to complete.
+	 */
+	for (j = 0; j < 9; j++) {
+		if (control & GPIO_I2C0_SCL)
+			write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW);
+		if (control & GPIO_I2C1_SCL)
+			write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW);
+		if (control & GPIO_I2C2_SCL)
+			write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW);
+		if (control & GPIO_I2C3_SCL)
+			write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW);
+
+		read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+		udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
+
+		if (control & GPIO_I2C0_SCL)
+			write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH);
+		if (control & GPIO_I2C1_SCL)
+			write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH);
+		if (control & GPIO_I2C2_SCL)
+			write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH);
+		if (control & GPIO_I2C3_SCL)
+			write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH);
+
+		read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
+		udelay(4);
+	}
+
+	/* Restore I2C pins. */
+	for (i = 0; i < saved_pins_count; i++)
+		restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
+}
+
 int gpio_interrupt_status(gpio_t gpio)
 {
 	uintptr_t gpio_address = gpio_get_address(gpio);