diff options
| author | Marshall Dawson <marshall.dawson@scarletltd.com> | 2018-08-03 17:05:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-08 17:51:27 +0000 |
| commit | 2e49cf129ac0f3326989cd1202904a3f02d1d467 (patch) | |
| tree | c7c3afb88c91194fe63d564cf68056923de70375 /src/soc/amd/stoneyridge/cpu.c | |
| parent | bd4a3f8cd9ec4c59ad1d33102958e525a9c8c6ef (diff) | |
amd/stoneyridge: Add warm reset detection
Extend the existing reset handling features in Stoney Ridge to plan for,
and recognize, warm resets. The ColdRstDet bit is always zero on a cold
reset, and is intended as a mechanism for the BIOS to determine the type
of a reset that occurred.
Set ColdRstDet=1 after all cores have been initialized, so that any
subsequent reset may be identified as warm/cold. A later patch will check
the value during mp_init.
Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/cpu.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 7fff1203aa..52b1c9cbb1 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -113,6 +113,8 @@ void stoney_init_cpus(struct device *dev) /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + set_warm_reset_flag(); } static void model_15_init(struct device *dev) |