amd/stoneyridge: Convert MP init to mp_init_with_smm

Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.

Add a new cpu.c file for most of the processor initiliazation.  Build
mp_ops with the necessary callbacks.  Note also that this patch removes
cpu_bus_scan.  Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.

SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time.  A later patch will add TSEG SMM
capabilities for the APU.

This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.

BUG=b:66200075

Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 4 insertions, 8 deletions

diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 14f76b7745..325d2ea82e 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -18,20 +18,16 @@
 #include <cpu/cpu.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <soc/southbridge.h>
+#include <soc/cpu.h>
 #include <soc/northbridge.h>
-
-static void cpu_bus_init(device_t dev)
-{
-	initialize_cpus(dev->link_list);
-}
+#include <soc/southbridge.h>
 
 struct device_operations cpu_bus_ops = {
 	.read_resources	  = DEVICE_NOOP,
 	.set_resources	  = DEVICE_NOOP,
 	.enable_resources = DEVICE_NOOP,
-	.init		  = &cpu_bus_init,
-	.scan_bus	  = cpu_bus_scan,
+	.init		  = stoney_init_cpus,
+	.scan_bus	  = NULL,
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
 };