diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2018-01-24 17:42:51 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-01-25 23:30:14 +0000 |
| commit | 51e4c1a76cafa0ddd429ffa78d0e6fdee179f731 (patch) | |
| tree | 1c540ebc0ba5a94ed9119b02be2e985597e5c2f9 /src/soc/amd/stoneyridge/bootblock | |
| parent | f49ddb67de5b6ff86ad080585bd835779521d647 (diff) | |
soc/amd/stoneyridge: remove dependence on TSC
The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.
BUG=b:72378235,b:72170796
Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/bootblock')
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock/bootblock.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 4b58287ba5..f9ae365c0d 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -28,6 +28,7 @@ #include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> +#include <timestamp.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -40,7 +41,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) if (!boot_cpu()) bootblock_soc_early_init(); /* APs will not return */ - bootblock_main_with_timestamp(base_timestamp); + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_timestamp(timestamp_get()); } /* Set the MMIO Configuration Base Address and Bus Range. */ |